The present invention relates to an interconnection structure of electronic parts and, particularly, to an interconnection structure of electronic parts using solder bumps.
By using an interconnection technology using solder bumps, a number of connection terminals can be interconnected at once. Therefore, such technology is suitable for interconnecting electronic parts each having a number of connection terminals and has been used widely in interconnecting LSI chips having, for example, several hundred of connecting terminals.
It has been known that, in a case where a bare-chip is connected to a substrate by using solder bumps, faults in connecting portions occur frequently. Bare-chip is an LSI chip not covered with insulating material. The reason for such faults is a difference in thermal expansion coefficient between the LSI chip and the substrate on which the LSI chip is mounted. The LSI chip generates heat during its operation, because of which the LSI chip and the substrate mounting the chip are expanded. Since their thermal expansion coefficients are different, stress is generated in the solder bumps interconnecting the LSI chip and the substrate. This stress is generated during operation of the LSI chip and disappears when the chip is inoperative. Therefore, generation of stress in the solder bumps is repeated, with which fatigue of the solder bumps occurs, leading to destruction thereof. As a result, the connecting portion or portions between the LSI chip and the substrate break.
An example of a technique for preventing such faults of the interconnection structure is disclosed in N. Matsui, et al. "VLSI CHIP INTERCONNECTION TECHNOLOGY USING STACKED SOLDER BUMPS", pp. 573 to 578, Proc. IEEE 37th Electronic Components Conf. In the technique disclosed in this article, stress in the solder bumps is reduced by stacking a plurality of solder bumps.
In this technique, however, the structure of the solder bumps is very complicated and difficult to manufacture.